1. Field of the Invention
The present invention relates to a circuit for generating a reset signal, and more particularly to a power-on reset circuit.
2. Description of the Related Art
For design of electronic circuits, a reset mechanism is normally added in these circuits so that these circuits can come back to an initial condition when necessary. Particularly at the beginning these electronic circuits being turned on, devices, such as registers, in these circuits are not stable, it is essential to reset the circuit to let these devices of these circuits be back to the initial condition.
Accordingly, a circuit is required to generate a reset signal at the beginning of the turn on of the circuit so that the state of the electronic circuit is in the initial condition. FIG. 1A is a drawing showing a traditional power-on reset circuit. Referring to FIG. 1A, when the power is not turned on, charges stored in the capacitor 112 are discharged through the resistor 111. At the beginning of the turn on of the power, the N-type transistor 114 is cut off. Accordingly, the power-on reset circuit in FIG. 1A can generate the reset signal RST by the pull-up resistor 113 and the buffer 115. A current is then provided through the resistor 110 to charge the capacitor 112 to result in the gate voltage of the transistor is higher than its threshold voltage. Then, the transistor 114 is turned on and disables the reset signal RST.
In order to make sure all devices can be reset, the time period of the enable reset signal of the power-on reset circuit must be long enough. In other words, the resistance-capacitance (RC) time delay formed by the resistor 110 and the capacitor 112 in FIG. 1A must be great enough. Accordingly, a big chip size is required. Moreover, the resistor 111 forms a leakage route that consumes unnecessary power.
U.S. Published Patent No. 2001/0028263 A1 titled “Power on reset circuit”, published on Oct. 11, 2001, discloses a power-on reset circuit as shown in FIG. 1B. In the power-on reset circuit 120, currents flowing through the transistor 121 are divided to the capacitor 123 and the transistor 122. Accordingly, the charging time of the capacitor 123 can be extended. The charge potential of the capacitor 123 can change the status of the inverter 124 to perform power-on reset. However, it is required to precisely control the current flowing through the transistor 122. If the current is too small, the time period of the reset signal cannot be enough; if the current is too large, the capacitor cannot be charged to the level that will change the status of the inverter 124. Moreover, the charging/discharging process will consume more power.
FIG. 1C is a power-on reset circuit disclosed in U.S. Pat. No. 6,388,479 titled “Oscillator based power-on reset circuit” on May 14, 2002. Referring to FIG. 1C, in the power-on reset circuit 130, the clock signal output from the oscillation circuit 131 passes directly through the transistor 132 and the capacitor 133 to affect the potential of the capacitor 133. When the potential of the capacitor 133 reaches the transitional critical point of the inverter 134, the power-on reset is performed. However, the RC time delay formed by the resistor of the transistor 132 and the capacitor 133 must be larger than the pulse width of the clock signal output from the oscillation circuit 131, otherwise the reset cannot be performed. In addition, the reset signal RST output from the power-on reset circuit 130 has the oscillation effect.
FIG. 1D is a power-on reset circuit disclosed in U.S. Pat. No. 5,386,152 titled “Power-on reset circuit responsive to a clock signal” on Jan. 31, 1995. Referring to FIG. 1D, in the power-on reset circuit 140, the charge/discharge signal provided from the positive/negative edge-triggered differentiator of the clock amplifier. Diodes are required to protect the circuit from the great reverse signal flowing from the ground terminal to the circuit. Accordingly, this circuit will generate noises through the substrate. In addition, the reset signal RST output from the power-on reset circuit 130 also has the oscillation effect.
FIG. 2 is a drawing showing the sequences of the power-on reset circuits of the prior arts described above and the present invention. Referring to FIG. 2, from top to bottom, the first line represents the power voltage VDD. The left side of the lines represents the transient changes when the power is turned on. The second line 120, the third line 130 and the fourth line 140 represent the reset signals output from the power-on reset circuits 120, 130 and 140, respectively. In this figure, with the same resistor and capacitor, the reset time period of the power-on reset circuit 120 is not sufficient. Though the reset time period output from the power-on reset circuit 130 is longer, there is a serious oscillation effect. The line 140a of the fourth line 140 represents the reset signal output from the power-on reset circuit 140. It still has the oscillation effect. In addition, the line 140b of the fourth line 140 shows that the signal with a voltage lower than the ground voltage in the internal of the power-on reset circuit 140.